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Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
Pin Description: Power-up Strapping Options
Certain pins are sampled upon power up or reset to initialize KSZ9692PB, KSZ9692PB-S system registers per system
configuration requirements.
Pin Number
E3
Pin Name
SADDR[0]
Pin Type
Ipd/O
Pin Description
During reset, this pin is the input strap option for NAND Boot small page size
0 = 512 Bytes (default)
1 = 528 Bytes
(Not support NAND Boot)
E1, E2
SADDR[2:1]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [7:6]. These pins are used to specify number of active
banks (CE#) in cascade.
00 = 1 bank (default)
01 = 2 banks
F4
SADDR[3]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [8], NAND Flash type. This pin is used to specify using
large or small block NAND Flash as a boot bank as follows:
“0” = small block (default)
“1” = large block
(Not support NAND Boot)
F5
SADDR[4]
Ipd/O
During reset, this pin is the input strap option for NAND Flash configuration
register (0x8054) bit [4], NAND Flash type. This pin is used to specify number
of NAND Flash in parallel for combined data width as follows:
“0” = 1 NAND Flash (default)
“1” = 2 NAND Flash
F3
SADDR[5]
Ipu/O
During reset, this is the input strap option to enter ARM9 tic test mode
0: ARM tic test mode (factory reserved)
1: Normal mode (default)
F2
SADDR[6]
Ipd/O
During reset, this pin is the input strap option for NAND FLASH device support
automatic page crossing
0: NAND FLASH device does not support automatic page crossing (default)
1: NAND FLASH device supports automatic page crossing
G1
SADDR[7]
Ipd/O
During reset, this pin is a strapping option for B0SIZE, Bank 0 Data Access
Size. This is applicable to ROM/SRAM/FLASH boot and NAND boot bank.
Bank 0 is used for boot program. This pin is used to specify the size of the bank
0 data bus width as follow:
“0” = one byte (default)
“1” = half word
F1
SADDR[8]
Ipd/O
During reset, this pin is a strapping option for BTSEL:
“0” = Boot select from NOR flash (default)
“1” = Boot select from NAND flash (Not support NAND Boot)
G2
SADDR[9]
Ipd/O
During reset this pin is a strapping option for BYP_SYSPLL:
“0” = Use systems PLL (default)
“1” = Bypass systems PLL, use external clock (factory reserved)
G4
SADDR[10]
Ipd/O
During reset this pin is a strapping option for BYP_CLKSEL:
“0” = Select 200MHz external clock (default)
“1” = Select 250MHz external clock (factory reserved)
May 2011
23
M9999-051111-4.0
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